Junction and device characteristics of gate-last ge p- and n-MOSFETs with ALD-Al2O3 gate dielectric

Chao Ching Cheng*, Chao-Hsin Chien, Guang Li Luo, Ching Lun Lin, Hung Sen Chen, Jun Cheng Liu, Chi Chung Kei, Chien Nan Hsiao, Chun Yen Chang

*Corresponding author for this work

研究成果: Article同行評審

16 引文 斯高帕斯(Scopus)

摘要

In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p+-n and n+-p junctions exceeded three and four orders of magnitude (in the voltage range of ±1 V), respectively, with accompanying reverse leakages of ca. 10-2 and 10-4 A · cm-2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 °C boosted the device on-current, decreased the Al2O3/Ge interface states to 8 × 1011cm-2 · eV-1, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm2 · V-1 · s-1 and 103, respectively, for the p-FET (W/L = 100 μm/ 4 μm), while these values were less than 100 cm2 · V-1 · s-1 and ca. 103, respectively, for the n-FET (W/L = 100 μm/9 μm). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.

原文English
頁(從 - 到)1681-1689
頁數9
期刊IEEE Transactions on Electron Devices
56
發行號8
DOIs
出版狀態Published - 16 七月 2009

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