JAIP-MP: A four-core Java application processor

Chun-Jen Tsai, Tsung Han Wu, Hung Cheng Su

研究成果: Conference contribution同行評審

摘要

In this paper, we present the design of a four-core Java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired Java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, Java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute Java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among Java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.

原文English
主出版物標題2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
發行者IEEE Computer Society
頁面189-194
頁數6
ISBN(電子)9781467391405
DOIs
出版狀態Published - 30 十月 2015
事件23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 - Daejeon, Korea, Republic of
持續時間: 5 十月 20157 十月 2015

出版系列

名字IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
2015-October
ISSN(列印)2324-8432
ISSN(電子)2324-8440

Conference

Conference23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
國家Korea, Republic of
城市Daejeon
期間5/10/157/10/15

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