In this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.
|頁（從 - 到）||13-17|
|期刊||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers|
|出版狀態||Published - 1 十二月 1996|
|事件||Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA|
持續時間: 10 十一月 1996 → 14 十一月 1996