Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)

Wen Yi Chen*, Ming-Dou Ker, Yeh Jen Huang

*Corresponding author for this work

研究成果: Article

17 引文 斯高帕斯(Scopus)

摘要

Latch-up is one of the most critical issues in high-voltage (HV) ICs due to the high power-supply voltages. Because the breakdown junction of an HV device is easily damaged by the huge power generated from a dc curve tracer, the device immunity against latch-up is often referred to the transmission-line-pulsing (TLP)-measured holding voltage. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-μm 18-V bipolar CMOS DMOS process to evaluate the validity of latch-up susceptibility by referring to the holding voltage measured by 100- and 1000-ns TLP systems and curve tracer. Long-pulse TLP measurement reveals the self-heating effect and self-heating speed of the n-channel LDMOS. The self-heating effect results in the TLP system to overestimate the holding voltage of HV n-channel LDMOS. Transient latch-up test is further used to investigate the susceptibility of HV devices to latch-up issue in field applications. As a result, to judge the latch-up susceptibility of HV devices by holding voltage measured from TLP is insufficient.

原文English
頁(從 - 到)762-764
頁數3
期刊IEEE Electron Device Letters
29
發行號7
DOIs
出版狀態Published - 1 七月 2008

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