Variability of nanoscale MOSFETs has been an obstacle to CMOS scaling. For future CMOS devices, hetero-channel using Ge or III-V compounds such as InGaAs have been proposed as performance boosters [1-2]. The variability, however, is further aggravated for these high-mobility materials due to their higher permittivity. The ultra-thin body (UTB) structure has been considered as a promising solution to improve device electrostatic integrity (EI) [3-4]. Using the UTB with thin buried oxide (BOX) structure also enables efficient threshold voltage (Vth) modulation via backgate bias (Vbg) [3-4] for power-performance optimization. In addition, the adaptive body bias (ABB) technique has been widely used to compensate the die-to-die variation [5-6], whereas the within-die Vth variation also changes with V bg. With the scaling of device dimensions, the quantum confinement (QC) effect may become significant and impact the pertinent V bg-dependence of Vth variability for the UTB hetero-channel devices. In this work, using TCAD atomistic simulation, we investigate the impact of Vbg on the intrinsic variability of gate line-edge-roughness (LER) for UTB SOI, GeOI, and InGaAs-OI MOSFETs considering quantum confinement.