Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling

Ming Long Fan, Vita Pi Ho Hu, Yin Nien Chen, Pin Su, Ching Te Chuang

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.

原文English
主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1130-1133
頁數4
ISBN(列印)9781479934324
DOIs
出版狀態Published - 1 一月 2014
事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
持續時間: 1 六月 20145 六月 2014

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家Australia
城市Melbourne, VIC
期間1/06/145/06/14

指紋 深入研究「Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling」主題。共同形成了獨特的指紋。

引用此