@inproceedings{aa32ee5b43024c4ca5c4c05dbada6183,
title = "Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling",
abstract = "In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.",
author = "Fan, {Ming Long} and Hu, {Vita Pi Ho} and Chen, {Yin Nien} and Pin Su and Chuang, {Ching Te}",
year = "2014",
month = jan,
day = "1",
doi = "10.1109/ISCAS.2014.6865339",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1130--1133",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",
note = "null ; Conference date: 01-06-2014 Through 05-06-2014",
}