Instruction-cycle-based dynamic voltage scaling power management for low-power digital signal processor with 53% power savings

Shen Yu Peng, Tzu Chi Huang, Yu Huei Lee, Chao Chang Chiu, Ke-Horng Chen, Ying Hsi Lin, Chao Cheng Lee, Tsung Yen Tsai, Chen Chih Huang, Long Der Chen, Cheng Chen Yang

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-μm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 Vμs saved 53% power.

原文English
文章編號6578600
頁數1
期刊IEEE Journal of Solid-State Circuits
48
發行號11
DOIs
出版狀態Published - 19 八月 2013

指紋 深入研究「Instruction-cycle-based dynamic voltage scaling power management for low-power digital signal processor with 53% power savings」主題。共同形成了獨特的指紋。

引用此