Independently-controlled-gate FinFET schmitt trigger sub-threshold SRAMs

Chien Yu Hsieh*, Ming Long Fan, Pi-Ho Hu, Pin Su, Ching-Te Chuang

*Corresponding author for this work

研究成果: Article同行評審

28 引文 斯高帕斯(Scopus)

摘要

In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG-ST) FinFET SRAM cells for sub-threshold operation. The proposed IG-ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG-ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS = 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (L eff, EOT, W fin, and H fin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of μ/σ ratio.

原文English
文章編號5875918
頁(從 - 到)1201-1210
頁數10
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
20
發行號7
DOIs
出版狀態Published - 七月 2012

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