Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices

Hao I. Yang*, Ching Te Chuang, Wei Hwang

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.

原文English
主出版物標題Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
頁面27-30
頁數4
DOIs
出版狀態Published - 25 十二月 2009
事件2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan
持續時間: 31 八月 20092 九月 2009

出版系列

名字Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Conference

Conference2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
國家Taiwan
城市Hsinchu
期間31/08/092/09/09

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