Impact of Nanoscale Polarization Relaxation on Endurance Reliability of One-Transistor Hybrid Memory Using Combined Storage Mechanisms

Yu Chien Chiu, Chun-Yen Chang, Hsiao-Hsuan Hsu, Chun-Hu Cheng, Min Hung Lee

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 10(12)-cycling endurance at 85 degrees C. Such excellent endurance reliability at 85 degrees C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.
原文English
主出版物標題IEEE International Reliability Physics Symposium (IRPS)
出版狀態Published - 2015

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