A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.
|出版狀態||Published - 1 一月 1996|
|事件||Proceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA|
持續時間: 13 六月 1996 → 15 六月 1996
|Conference||Proceedings of the 1996 Symposium on VLSI Circuits|
|城市||Honolulu, HI, USA|
|期間||13/06/96 → 15/06/96|