IDCT processor on the adder-based distributed arithmetic

Chingson Chen*, Tian-Sheuan Chang, Chein Wei Jen

*Corresponding author for this work

研究成果: Paper同行評審

5 引文 斯高帕斯(Scopus)

摘要

A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.

原文English
頁面36-37
頁數2
出版狀態Published - 1 一月 1996
事件Proceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA
持續時間: 13 六月 199615 六月 1996

Conference

ConferenceProceedings of the 1996 Symposium on VLSI Circuits
城市Honolulu, HI, USA
期間13/06/9615/06/96

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