Hybrid testbench acceleration for reducing communication overhead

Chin Lung Chuang, Chien-Nan Liu*

*Corresponding author for this work

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57 hardware overhead.

原文English
文章編號5739840
頁(從 - 到)40-50
頁數11
期刊IEEE Design and Test of Computers
28
發行號2
DOIs
出版狀態Published - 1 三月 2011

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