High-R Poly Resistance Deviation Improvement from Suppressions of Back-End Mechanical Stresses

Tingyou Lin, Yingchieh Ho*, Chau-Chin Su

*Corresponding author for this work

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper investigates techniques for N-Type high-resistance polysilicon resistors to reduce the resistance deviation which is caused by the back-end mechanical stress. In the back-end layers of the wafer, a top metal thickness equal to 3μm is provided to increase the heat allowing current density in the metal routes of power ICs. The top metal processing yields the mechanical stress to increase the resistance by the piezoresistance effect. To eliminate the mechanical stresses, a new layout is proposed with the full passivation cutting (FPC). The resistor with an FPC uses the passivation film separation to create a physical empty room for suppressing the mechanical stresses on the polysilicon. The proposed layout has been verified in the 0.4-μm bipolar-CMOS-DMOS process, and the resistance shifts were compared with other four-Type layouts. Compared to those original layouts, the proposed layout exhibits the improvements in the resistance deviation reduction in the maximum ratio 20.80%.

原文English
文章編號8026567
頁(從 - 到)4233-4241
頁數9
期刊IEEE Transactions on Electron Devices
64
發行號10
DOIs
出版狀態Published - 1 十月 2017

指紋 深入研究「High-R Poly Resistance Deviation Improvement from Suppressions of Back-End Mechanical Stresses」主題。共同形成了獨特的指紋。

引用此