High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications

Po Jung Sung, Ta Chun Cho, Fu Ju Hou, Fu Kuo Hsueh, Sheng Ti Chung, Yao Jen Lee, Michael I. Current, Tien-Sheng Chao

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S.S.) of 65 mV/decade with I ON I OFF >10 9 ; strained JL bulk FinFETs show an S.S. of 75 mV/decade with I ON I OFF >10 7 . For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by I D -V G curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher I D and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.

原文English
文章編號7885526
頁(從 - 到)2054-2060
頁數7
期刊IEEE Transactions on Electron Devices
64
發行號5
DOIs
出版狀態Published - 1 五月 2017

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