High-performance GaN MOSFET with high-κ LaAlO 3/SiO 2 gate dielectric

Chung-Yong Tsai; T. L. Wu; Albert Chin

doi:10.1109/LED.2011.2172911

High-performance GaN MOSFET with high-κ LaAlO ₃/SiO ₂ gate dielectric

Chung-Yong Tsai^*, T. L. Wu, Albert Chin

^*Corresponding author for this work

研究成果: Article › 同行評審

75 引文斯高帕斯（Scopus）

摘要

Using a high-κ LaAlO ₃/SiO ₂ gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V _t) of 0.1 V, low on-resistance (R _on) of 13.5 Ω mm, high breakdown voltage of 385 V, high transconductance (g _m) of 136 mS/mm, and record-best normalized drive current (μ C _ox) of 172 μA/V ². Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-κ gate dielectric and recessed-gate etching.

原文	English
文章編號	6087370
頁（從 - 到）	35-37
頁數	3
期刊	IEEE Electron Device Letters
卷	33
發行號	1
DOIs	https://doi.org/10.1109/LED.2011.2172911
出版狀態	Published - 1 一月 2012

存取文件

10.1109/LED.2011.2172911

其它文件與鏈接

Link to publication in Scopus

指紋深入研究「High-performance GaN MOSFET with high-κ LaAlO <sub>3</sub>/SiO <sub>2</sub> gate dielectric」主題。共同形成了獨特的指紋。

引用此

@article{c1c206724a5b45da935aa1076bc2abbb,

title = "High-performance GaN MOSFET with high-κ LaAlO 3/SiO 2 gate dielectric",

abstract = "Using a high-κ LaAlO 3/SiO 2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V t) of 0.1 V, low on-resistance (R on) of 13.5 Ω mm, high breakdown voltage of 385 V, high transconductance (g m) of 136 mS/mm, and record-best normalized drive current (μ C ox) of 172 μA/V 2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-κ gate dielectric and recessed-gate etching.",

keywords = "GaN, high κ, LaAlO, MOSFET",

author = "Chung-Yong Tsai and Wu, {T. L.} and Albert Chin",

year = "2012",

month = jan,

day = "1",

doi = "10.1109/LED.2011.2172911",

language = "English",

volume = "33",

pages = "35--37",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - High-performance GaN MOSFET with high-κ LaAlO 3/SiO 2 gate dielectric

AU - Tsai, Chung-Yong

AU - Wu, T. L.

AU - Chin, Albert

PY - 2012/1/1

Y1 - 2012/1/1

N2 - Using a high-κ LaAlO 3/SiO 2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V t) of 0.1 V, low on-resistance (R on) of 13.5 Ω mm, high breakdown voltage of 385 V, high transconductance (g m) of 136 mS/mm, and record-best normalized drive current (μ C ox) of 172 μA/V 2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-κ gate dielectric and recessed-gate etching.

AB - Using a high-κ LaAlO 3/SiO 2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V t) of 0.1 V, low on-resistance (R on) of 13.5 Ω mm, high breakdown voltage of 385 V, high transconductance (g m) of 136 mS/mm, and record-best normalized drive current (μ C ox) of 172 μA/V 2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-κ gate dielectric and recessed-gate etching.

KW - GaN

KW - high κ

KW - LaAlO

KW - MOSFET

UR - http://www.scopus.com/inward/record.url?scp=84655166497&partnerID=8YFLogxK

U2 - 10.1109/LED.2011.2172911

DO - 10.1109/LED.2011.2172911

M3 - Article

AN - SCOPUS:84655166497

VL - 33

SP - 35

EP - 37

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 1

M1 - 6087370

ER -