High-performance charge-trapping flash memory device with an ultrathin 2.5-nm equivalent-Si 3N 4-thickness trapping layer

Chung-Yong Tsai; Albert Chin

doi:10.1109/TED.2011.2171970

High-performance charge-trapping flash memory device with an ultrathin 2.5-nm equivalent-Si ₃N ₄-thickness trapping layer

Chung-Yong Tsai^*, Albert Chin

^*Corresponding author for this work

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

摘要

We made the MoN-[SiO ₂-LaAlO ₃]-[Ge-HfON]-[LaAlO ₃-SiO ₂]-Si charge-trapping (CT) Flash device with a record-thinnest 2.5-nm equivalent-Si ₃N ₄-thickness trapping layer, a large 4.4-V initial memory window, a 3.2-V ten-year extrapolated retention window at 125 °C, and a 3.6-V endurance window at 10 ⁶ cycles, under very fast 100 μs and low ± 16-V program/erase pulses. These were achieved using Ge reaction with a HfON trapping layer for better CT and retention.

原文	English
文章編號	6078413
頁（從 - 到）	252-254
頁數	3
期刊	IEEE Transactions on Electron Devices
卷	59
發行號	1
DOIs	https://doi.org/10.1109/TED.2011.2171970
出版狀態	Published - 1 一月 2012

存取文件

10.1109/TED.2011.2171970

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引用此

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