High-performance charge-trapping flash memory device with an ultrathin 2.5-nm equivalent-Si 3N 4-thickness trapping layer

Chung-Yong Tsai*, Albert Chin

*Corresponding author for this work

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

We made the MoN-[SiO 2-LaAlO 3]-[Ge-HfON]-[LaAlO 3-SiO 2]-Si charge-trapping (CT) Flash device with a record-thinnest 2.5-nm equivalent-Si 3N 4-thickness trapping layer, a large 4.4-V initial memory window, a 3.2-V ten-year extrapolated retention window at 125 °C, and a 3.6-V endurance window at 10 6 cycles, under very fast 100 μs and low ± 16-V program/erase pulses. These were achieved using Ge reaction with a HfON trapping layer for better CT and retention.

原文English
文章編號6078413
頁(從 - 到)252-254
頁數3
期刊IEEE Transactions on Electron Devices
59
發行號1
DOIs
出版狀態Published - 1 一月 2012

指紋 深入研究「High-performance charge-trapping flash memory device with an ultrathin 2.5-nm equivalent-Si <sub>3</sub>N <sub>4</sub>-thickness trapping layer」主題。共同形成了獨特的指紋。

引用此