High gain and low noise single balanced wireless receiver front-end circuit design

Zhe Yang Huang*, Che Cheng Huang, Jung Mao Lin, Chung-Chih Hung

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

原文English
主出版物標題Innovation for Applied Science and Technology
頁面2647-2651
頁數5
DOIs
出版狀態Published - 20 二月 2013
事件2nd International Conference on Engineering and Technology Innovation 2012, ICETI 2012 - Kaohsiung, Taiwan
持續時間: 2 十一月 20126 十一月 2012

出版系列

名字Applied Mechanics and Materials
284-287
ISSN(列印)1660-9336
ISSN(電子)1662-7482

Conference

Conference2nd International Conference on Engineering and Technology Innovation 2012, ICETI 2012
國家Taiwan
城市Kaohsiung
期間2/11/126/11/12

指紋 深入研究「High gain and low noise single balanced wireless receiver front-end circuit design」主題。共同形成了獨特的指紋。

引用此