High-aspect ratio through silicon via (TSV) technology

H. B. Chang*, H. Y. Chen, P. C. Kuo, Chao-Hsin Chien, E. B. Liao, T. C. Lin, T. S. Wei, Y. C. Lin, Y. H. Chen, K. F. Yang, H. A. Teng, W. C. Tsai, Y. C. Tseng, S. Y. Chen, C. C. Hsieh, M. F. Chen, Y. H. Liu, T. J. Wu, Shang Y. Hou, W. C. ChiouS. P. Jeng, C. H. Yu

*Corresponding author for this work

研究成果: Conference contribution同行評審

20 引文 斯高帕斯(Scopus)

摘要

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

原文English
主出版物標題2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
頁面173-174
頁數2
DOIs
出版狀態Published - 27 九月 2012
事件2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
持續時間: 12 六月 201214 六月 2012

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
ISSN(列印)0743-1562

Conference

Conference2012 Symposium on VLSI Technology, VLSIT 2012
國家United States
城市Honolulu, HI
期間12/06/1214/06/12

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