Hierarchical instruction encoding for VLIW digital signal processors

Chia Hsien Liu, Tay Jyi Lin, Chie Min Chao, Pi Chen Hsiao, Li Chun Lin, Shin Kai Chen, Chao Wei Huang, Chih-Wei Liu, Chein Wei Jen

研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)

摘要

VLIW-based architectures are very popular in highperformance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixedlength instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%̃66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.

原文English
文章編號1465384
頁(從 - 到)3503-3506
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 1 十二月 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 五月 200526 五月 2005

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