Hardware efficient transform designs with cyclic formulation and subexpression sharing

Tian-Sheuan Chang*, Chein Wei Jen

*Corresponding author for this work

研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)

摘要

This paper presents a hardware efficient architecture for transform designs. Unlike other designs that use systolic array and memory-based design, the proposed architecture exploited the constant property of the transform coefficients as well as their numerical property. The proposed design reformulates the transform with cyclic convolution such that filter type subexpression sharing can be applied to reduce the area cost. The results show that the new designs can save up to 81% gate area cost compared with previous designs for 5-point DVF designs.

原文English
頁(從 - 到)398-401
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
DOIs
出版狀態Published - 1 一月 1998
事件Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
持續時間: 31 五月 19983 六月 1998

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