This paper presents a hardware efficient architecture for transform designs. Unlike other designs that use systolic array and memory-based design, the proposed architecture exploited the constant property of the transform coefficients as well as their numerical property. The proposed design reformulates the transform with cyclic convolution such that filter type subexpression sharing can be applied to reduce the area cost. The results show that the new designs can save up to 81% gate area cost compared with previous designs for 5-point DVF designs.
|頁（從 - 到）||398-401|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 一月 1998|
|事件||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
持續時間: 31 五月 1998 → 3 六月 1998