Hardware-efficient pipelined programmable FIR filter design

Tian-Sheuan Chang*, C. W. Jen

*Corresponding author for this work

研究成果: Article

2 引文 斯高帕斯(Scopus)

摘要

With the increasing demand for video-signal processing and transmission, high-speed programmable FIR filters are required for real-time processing. This paper presents a hardware-efficient pipelined FIR architecture with programmable coefficients. FIR operations are first reformulated into multi-bit DA form at an algorithm level. Then, at the architecture level, the (p, q) compressor, instead of Booth encoding or RAM implementation, is used for high-speed operation. Due to the simple architecture, we can easily pipeline the proposed FIR filter to the adder level and save up to half of the cost of previous designs without sacrificing performance. The presented design is useful for bit-parallel input design, which can save 36.7% of the area cost compared with previous approaches.

原文English
頁(從 - 到)227-232
頁數6
期刊IEE Proceedings: Computers and Digital Techniques
148
發行號6
DOIs
出版狀態Published - 1 十一月 2001

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