Hardware-assisted syntax decoding model for software AVC/H.264 decoders

Ming Ju Wu*, Yi Tseng Chen, Chun-Jen Tsai

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of AVC/H.264 standard (for both CAVLC and CABAC acceleration). Nevertheless, the design of the proposed syntax decoding model has the potential of becoming the design of a flexible bitstream parser, which is the most challenging problem in the MPEG Reconfigurable Video Coding (RVC) Framework. A Virtex-5 FPGA development board is used to implement and verify the full hardware-software system (including the hardware entropy engines and the software syntax parser and macroblock data reconstruction modules extracted from JM12.2).

原文English
主出版物標題2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面1233-1236
頁數4
DOIs
出版狀態Published - 26 十月 2009
事件2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
持續時間: 24 五月 200927 五月 2009

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家Taiwan
城市Taipei
期間24/05/0927/05/09

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