Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC

Fang Ting Chou, Chung-Chih Hung

研究成果: Article同行評審

16 引文 斯高帕斯(Scopus)

摘要

This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary-weighted current switches in a current-steering digital-to-analog converter (DAC). The method was proved successfully by a 10-bit 400-MHz pure binary-weighted current-steering DAC with a minimum number of retiming latches. The experiment results yield very low-glitch energy during major carry transitions at output, which is < 1 pVs. This brief utilizes a layout structure to improve the spurious-free dynamic range at high signal frequencies. This chip was implemented in a standard 0.18-μm CMOS technology and consumes 20.7 mW at 400 MS/s.

原文English
文章編號7360216
頁(從 - 到)2407-2411
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
24
發行號6
DOIs
出版狀態Published - 1 六月 2016

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