General approach to design VLSI arrays for the multi-dimensional discrete Hartley transform

Jiun-In  Guo*, Chi Min Liu, Chein Wei Jen

*Corresponding author for this work

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, a general memory-based approach to design VLSI arrays for the multi-dimensional (M-D) discrete Hartley transform (DHT) with any length is proposed. There are four parts of this approach: (1) a new M-D DHT formulation, (2) cyclic convolution representation, (3) systolic array realization, and (4) memory-based implementation. Deriving a new M-D DHT formulation avoids the undesirable overhead required in formal designs [1, 2, 3, 4]. Taking cyclic convolution provides high computing parallelism and low computation complexity. Using systolic array realization results in high computing speeds and low I/O cost. Adopting the memory-based implementation yields low hardware cost and low power dissipation. In summary, the proposed approach will lead to efficient and high-performance VLSI array designs for the M-D DHT.

原文English
頁(從 - 到)235-238
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
DOIs
出版狀態Published - 1 十二月 1994
事件Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
持續時間: 30 五月 19942 六月 1994

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