In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D doping abruptness requirements for gate length scaling are examined. VT control will be challenging as a single gate material for both NMOS and PMOS devices cannot provide low yet symmetrical VT's. CMOS integration will thus require dual gate workfunction tuning, channel doping, or asymmetrical double-gates to adjust VT. Advantages of using alternative channel materials to facilitate scaling are investigated.
|頁（從 - 到）||719-722|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1 十二月 2000|
|事件||2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States|
持續時間: 10 十二月 2000 → 13 十二月 2000