Gate-induced drain leakage in LDD and fully-overlapped LDD MOSFETs

S. Parke*, J. Moon, P. Nee, J. Huang, Chen-Ming Hu, P. K. Ko

*Corresponding author for this work

研究成果: Conference article同行評審

6 引文 斯高帕斯(Scopus)

摘要

It is shown that lightly doped drain (LDD) devices exhibit substantial reductions in gate-induced drain leakage (GIDL) current as compared with the conventional single-drain (SD) device. The fully overlapped LDD structure can exhibit low GIDL approaching that of the nonoverlapped LDD as the n- concentration is increased toward 1 × 1019/cm3. A longer n- spacer also helps reduce GIDL in the fully overlapped devices. These GIDL design constraints must be weighed against the hot-electron reliability and device performance constraints in order to optimize the drain design.

原文English
頁(從 - 到)49-50
頁數2
期刊Digest of Technical Papers - Symposium on VLSI Technology
DOIs
出版狀態Published - 1 十二月 1991
事件1991 Symposium on VLSI Technology - Oiso, Jpn
持續時間: 28 五月 199130 五月 1991

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