摘要
Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.
原文 | English |
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頁面 | 397-400 |
頁數 | 4 |
DOIs | |
出版狀態 | Published - 1 一月 1997 |
事件 | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn 持續時間: 28 一月 1997 → 31 一月 1997 |
Conference
Conference | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC |
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城市 | Chiba, Jpn |
期間 | 28/01/97 → 31/01/97 |