Fuzzy-based circuit partitioning in built-in current testing

Wang Dauh Tseng*, Kuo-Chen Wang

*Corresponding author for this work

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.

原文English
頁面397-400
頁數4
DOIs
出版狀態Published - 1 一月 1997
事件Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
持續時間: 28 一月 199731 一月 1997

Conference

ConferenceProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
城市Chiba, Jpn
期間28/01/9731/01/97

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