During manufacture of wire bonding in packaged IC products, the breaking of bond wires and the peeling of bond pads occur frequently. The result is open-circuit failure in IC products. There were several prior methods reported to overcome these problems by using additional process flows or special materials. In this paper, a layout method is proposed to improve the bond wire reliability in general CMOS processes. By changing the layout patterns of bond pads, the reliability of bond wires on bond pads can be improved. A set of different layout patterns of bond pads has been drawn and fabricated in a 0.6-μm single-poly triple-metal CMOS process for investigation by the bond wire reliability tests, the ball shear test and the wire pull test. By implementing effective layout patterns on bond pads in packaged IC products, not only the bond wire reliability can be improved, but also the bond pad capacitance can be reduced for high frequency application. The proposed layout method for bond pad design is fully process-compatible to general CMOS processes.
|頁（從 - 到）||309-316|
|期刊||IEEE Transactions on Components and Packaging Technologies|
|出版狀態||Published - 1 六月 2002|