Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead

Wen Quan He, Yu Chun Lin, Jui Yi Hung, Shyh-Jye Jou

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper proposes a novel full-digital architecture of adaptive decision feedback equalizer (ADFE) for wireline 2-level pulse amplitude modulation (2-PAM) systems. It is well known that the feedback loop in DFE limits the greatest achievable speed. The proposed scheme begins by deriving coefficient-lookahead concept based on a reasonable assumption, whereupon a preliminary architecture can be implemented using the formula derived. Furthermore, according to channel characteristics, the formula derived can be simplified to break the feedback loop. Finally, the architecture can be easily pipelined and processed in parallel to achieve high throughput rate. Thus, the proposed design is a high speed design with parallel and pipeline architecture. This paper used a TSMC 40 nm CMOS process to fabricate the proposed design with a build-in self-test (BIST) circuit. The measured results show that the throughput rate is up to 16 Gbps.

原文English
主出版物標題Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
編輯Junyan Ren, Ting-Ao Tang, Fan Ye, Huihua Yu
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479984831
DOIs
出版狀態Published - 21 七月 2016
事件11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
持續時間: 3 十一月 20156 十一月 2015

出版系列

名字Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

Conference

Conference11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
國家China
城市Chengdu
期間3/11/156/11/15

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