Formal compliance verification of interface protocols

Ya Ching Yang*, Juinn-Dar Huang, Chia Chih Yen, Che Hua Shih, Jing Yang Jou

*Corresponding author for this work

研究成果: Conference contribution同行評審

7 引文 斯高帕斯(Scopus)

摘要

Verifying whether a building block conforms to certain interface protocol is one of the important steps while constructing an SoC. However, most existing methods have their own limitations. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel branch-and-bound algorithm for interface protocol compliance verification. The properties of the interface protocol are specified as a specification FSM, and the interface logic is formally verified at the higher FSM level. Using the FSM for property specification is relatively systematic than using other proprietary property languages, which greatly reduces the possibility of incomplete property identification. And it is shown theoretically and experimentally that the proposed algorithm can finish in reasonable time complexity.

原文English
主出版物標題2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
頁面12-15
頁數4
DOIs
出版狀態Published - 1 十二月 2005
事件2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
持續時間: 27 四月 200529 四月 2005

出版系列

名字2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
國家Taiwan
城市Hsinchu
期間27/04/0529/04/05

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