Flicker-noise impact on scaling of mixed-signal CMOS with HfSiON

Yuri Yasuda*, Tsu Jae King Liu, Chen-Ming Hu

*Corresponding author for this work

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

The flicker noise in MOSFETs with short gate lengths (L ≤ 1 μm) is severely degraded by the presence of a thick high-k gate dielectric layer. The gate length dependence of flicker noise becomes stronger with increasing high-k dielectric thickness - but only for n-FET. To explain these phenomena, a model based on excess traps at the gate edges has been developed. This model explains the flicker-noise dependence on high-k dielectric thickness and gate length and has successfully reproduced the experimental data. Based on the model, the impact of gate-length scaling is evaluated for future mixed-signal ICs using high-k gate-dielectric technology. The deployment of high-k gate dielectric adds another gate-length-scaling limit for analog devices due to the noise consideration.

原文English
頁(從 - 到)417-422
頁數6
期刊IEEE Transactions on Electron Devices
55
發行號1
DOIs
出版狀態Published - 1 一月 2008

指紋 深入研究「Flicker-noise impact on scaling of mixed-signal CMOS with HfSiON」主題。共同形成了獨特的指紋。

引用此