First experimental Ge CMOS FinFETs directly on SOI substrate

Cheng Ting Chung*, Che Wei Chen, Jyun Chih Lin, Che Chen Wu, Chao-Hsin Chien, Guang Li Luo

*Corresponding author for this work

研究成果: Conference contribution同行評審

9 引文 斯高帕斯(Scopus)

摘要

High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of Lchannel =120nm and Fin width=40nm with high Ion/Ioff ratio (>105), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n-and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.

原文English
主出版物標題2012 IEEE International Electron Devices Meeting, IEDM 2012
DOIs
出版狀態Published - 1 十二月 2012
事件2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
持續時間: 10 十二月 201213 十二月 2012

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
ISSN(列印)0163-1918

Conference

Conference2012 IEEE International Electron Devices Meeting, IEDM 2012
國家United States
城市San Francisco, CA
期間10/12/1213/12/12

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