First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Chao Ching Cheng, Yun Yan Chung, Uing Yang Li, Chao Ting Lin, Chi Feng Li, Jyun Hong Chen, Tung Yen Lai, Kai Shin Li, Jia Min Shieh, Sheng Kai Su, Hung Li Chiang, Tzu Chiang Chen, Lain Jong Li, H. S.Philip Wong, Chao-Hsin Chien*

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL.

原文English
主出版物標題2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T244-T245
頁數2
ISBN(電子)9784863487178
DOIs
出版狀態Published - 六月 2019
事件39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan
持續時間: 9 六月 201914 六月 2019

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2019-June
ISSN(列印)0743-1562

Conference

Conference39th Symposium on VLSI Technology, VLSI Technology 2019
國家Japan
城市Kyoto
期間9/06/1914/06/19

指紋 深入研究「First demonstration of 40-nm channel length top-gate WS<sub>2</sub> pFET using channel area-selective CVD growth directly on SiO<sub>x</sub>/Si substrate」主題。共同形成了獨特的指紋。

引用此