While the selection of new “backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFET with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm. These MOSFETs are believed to be the smallest double-gate transistors ever fabricated. Excellent short-channel performance is observed in devices with a wide range of gate lengths (10∼105 nm). The subthreshold slopes of the 10nm gate length FinFETs are 125mV/dec for n-FET and 101mV/dec for p-FET, respectively. The DIBL’s are 71mV/V for n-FET and 120mV/V for p-FET, respectively. At 55 nm gate length, the subthreshold slopes are 64mV/dec for n-FET and 68mV/dec for p-FET, which is very close to the ideal MOSFET behavior (at room temperature). The DIBL’s are 11mV/V for n-FET and 27mV/V for p-FET, respectively. All measurements were performed at a supply voltage of 1.2V. The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs. Due to the (110) channel crystal orientation, hole mobility in the fabricated p-channel FinFET remarkably exceeds that in a traditional planar MOSFET. At 105 nm gate length, p-channel FinFET shows a record-high transconductance of 633μS/μm at a Vdd of 1.2V. At extremely small gate lengths, parasitic Rsd in the narrow fin (proportionally scaled with Lg) influences the device performance. Working CMOS FinFET inverters are also demonstrated.
|頁（從 - 到）||251-254|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1 一月 2002|