Exploration of inter-die bulk fin-typed field effect transistor process variation for reduction of device variability

Ping Hsun Su, Yi-ming Li*

*Corresponding author for this work

研究成果: Article同行評審

摘要

This work first reports a novel exploration technique to systematically prioritize key fabrication in-line process parameters of 16-nm high-k metal gate (HKMG) bulk FinFET to reduce device's die-to-die variation. To extract hidden correlations and reduce decision variables among the complex in-line process parameters, a data mining technique is employed to highlight and group associated parameters. To correlate the measured data with the distribution of physical dimension of devices for all in-line processes, a sensitivity analysis is then performed. Because the variability of current process deeply affects the next process, so the sequence of fabrication process is further added into the analyzing procedure to increase the searching efficiency. The source of variation of the initial process can be monitored and traced by the proposed methodology. The result of this study indicates that the gate spacer is a key process factor and will determine the uniformity of process including, such as the source-and-drain proximity, and the depth, lateral offset and overlap of sequential doping implants. The ranked key in-line process parameters can be used to optimize process and minimize the device variability of 16-nm HKMG bulk FinFET devices.

原文English
頁(從 - 到)6124-6130
頁數7
期刊Journal of Nanoscience and Nanotechnology
16
發行號6
DOIs
出版狀態Published - 1 六月 2016

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