Experimental demonstration of performance enhancement of MFMIS and MFIS for 5-nm × 12.5-nm poly-Si nanowire gate-all-around negative capacitance FETs featuring seed-layer and PMA-free process

Shen Yang Lee, Han Wei Chen, Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Yu En Huang, Hsin Yu Chen, Tien Sheng Chao

研究成果: Conference contribution同行評審

摘要

We have experimentally demonstrated fully suspended nanowire (NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm × 12.5 -nm); they exhibit a remarkable Ion-Ioff ratio of over 1010. This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S min of 39.22 mV/decade. A ZrO2 seed-layer is inserted under HfZr 1-x, Ox(HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current (IG) is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.

原文English
主出版物標題2019 Silicon Nanoelectronics Workshop, SNW 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9784863487024
DOIs
出版狀態Published - 六月 2019
事件24th Silicon Nanoelectronics Workshop, SNW 2019 - Kyoto, Japan
持續時間: 9 六月 201910 六月 2019

出版系列

名字2019 Silicon Nanoelectronics Workshop, SNW 2019

Conference

Conference24th Silicon Nanoelectronics Workshop, SNW 2019
國家Japan
城市Kyoto
期間9/06/1910/06/19

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