Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling

Kai Chen*, Chen-Ming Hu, Peng Fang, Ashawant Gupta

*Corresponding author for this work

研究成果: Article同行評審

16 引文 斯高帕斯(Scopus)

摘要

MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 μm have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators' load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted.

原文English
頁(從 - 到)275-277
頁數3
期刊IEEE Electron Device Letters
18
發行號6
DOIs
出版狀態Published - 1 六月 1997

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