Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices

Tse Ching Wu, Chien Ju Chen, Yin Nien Chen, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

研究成果: Conference contribution同行評審

摘要

In this paper, we investigate the hybrid TFET-FinFET 32-bit carry-look-ahead adder (CLA) circuit and compare the delay, power and power-delay product (PDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. In the hybrid design, TFETs are used for the top critical path to reduce the longest path delay, and FinFETs are used for the rest of the circuit to reduce switching power and leakage power. The PDP of the hybrid TFET-FinFET CLA circuit is better than the circuits with all FinFET and all TFET implementations in the vicinity of VDD=0.3V. However, as the operating voltage is further reduced, the lower-ranked critical paths (e.g. 2nd critical path) with some FinFET devices in the path stick out, and the delay and PDP become inferior to all TFET implementation.

原文English
主出版物標題2015 International Conference on IC Design and Technology, ICICDT 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479976690
DOIs
出版狀態Published - 23 七月 2015
事件International Conference on IC Design and Technology, ICICDT 2015 - Leuven, Belgium
持續時間: 1 六月 20153 六月 2015

出版系列

名字2015 International Conference on IC Design and Technology, ICICDT 2015

Conference

ConferenceInternational Conference on IC Design and Technology, ICICDT 2015
國家Belgium
城市Leuven
期間1/06/153/06/15

指紋 深入研究「Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices」主題。共同形成了獨特的指紋。

引用此