ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

Ming-Dou Ker, Chyh Yih Chang, Yi Shu Chang

研究成果: Conference contribution同行評審

8 引文 斯高帕斯(Scopus)

摘要

This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 μm between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.

原文English
主出版物標題Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
編輯John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
發行者Institute of Electrical and Electronics Engineers Inc.
頁面234-238
頁數5
ISBN(電子)0780374940
DOIs
出版狀態Published - 1 一月 2002
事件15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
持續時間: 25 九月 200228 九月 2002

出版系列

名字Proceedings of the Annual IEEE International ASIC Conference and Exhibit
2002-January
ISSN(列印)1063-0988

Conference

Conference15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
國家United States
城市Rochester
期間25/09/0228/09/02

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