ESD protection design for 1- To 10-GHz distributed amplifier in CMOS technology

Ming-Dou Ker*, Yuan Wen Hsiao, Bing Jye Kuo

*Corresponding author for this work

研究成果: Article同行評審

20 引文 斯高帕斯(Scopus)

摘要

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-μm CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7±1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9±1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.

原文English
頁(從 - 到)2672-2681
頁數10
期刊IEEE Transactions on Microwave Theory and Techniques
53
發行號9
DOIs
出版狀態Published - 1 九月 2005

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