ESD implantations for on-chip ESD protection with layout consideration in 0.18-μm salicided CMOS technology

Ming-Dou Ker*, Che Hao Chuang, Wen Yu Lo

*Corresponding author for this work

研究成果: Article同行評審

22 引文 斯高帕斯(Scopus)

摘要

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-μm salicided CMOS process is investigated by experimental testchips. The second breakdown current (I t2 ) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.

原文English
頁(從 - 到)328-337
頁數10
期刊IEEE Transactions on Semiconductor Manufacturing
18
發行號2
DOIs
出版狀態Published - 1 五月 2005

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