Energy efficient intra-task dynamic voltage scaling for realistic CPUs of mobile devices

Chien Chung Yang*, Kuo-Chen Wang, Ming Ham Lin, Pochun Lin

*Corresponding author for this work

研究成果: Article

5 引文 斯高帕斯(Scopus)

摘要

It is not energy efficient to run a CPU at full speed all the time for all kinds of tasks in mobile devices. This paper proposes two energy efficient intra-task dynamic voltage scaling (DVS) algorithms for CPUs. There are three main contributions in this paper. Firstly, unlike the tedious derivation in PACE [2], we have derived the same optimal speed schedule with minimal energy consumption in a discrete and elegant way by using the Lagrange multiplier procedure. Secondly, the CPU model assumed in PACE is ideal, meaning that such a CPU supports all possible frequencies/voltage levels. We call such CPUs as ideal CPUs. In reality, CPUs only support a limited set of frequency/voltage levels, and we call this kind of CPUs as realistic CPUs. Thirdly, since energy consumption is not a simple function of frequency, it is more reasonable to transform the original nonlinear programming problem to the Multiple-Choice Knapsack Problem (MCKP). Since the problem can be described by a multistage graph, we used dynamic programming to derive an Optimal Schedule for Realistic CPUs (OSRC) with minimal energy consumption for realistic CPUs by using actual power consumption specifications of realistic CPUs. Considering potential computation and transition overheads, we have also proposed a low overhead OSRC (LO-OSRC), which restricts the change of CPU frequency/voltage to only once in the speed schedule. By using actual data from the power consumption specifications of two classical CPUs for evaluation, experimental results have shown that the energy saving of the proposed OSRC (LO-OSRC) is up to 10.3% (9.4%) better than that of PACE for realistic CPUs.

原文English
頁(從 - 到)251-272
頁數22
期刊Journal of Information Science and Engineering
25
發行號1
DOIs
出版狀態Published - 1 一月 2009

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