In this paper, a low-power and high-speed ternary content addressable memory (TCAM) macro design is presented. It employs the concept of architecture and circuit co-design. For achieving an energy-efficient TCAM architecture, the hierarchy search-line scheme and butterfly match-line scheme are proposed. The hierarchy search-line scheme realizes more power reduction by decreasing not only switching activities but also capacitance on search lines. The butterfly match-line scheme connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. Moreover, the match-lines are also implemented by a noise-tolerant XOR-based conditional keeper to reduce not only search time but power consumption. Furthermore, in order to reduce increasing leakage power with advanced technologies, the proposed TCAM design employs a super cut-off power gating technique and multi-mode data-retention power gating technique to reduce leakage currents. These two techniques can reduce cell leakage power significantly in standby mode. In addition to the super cut-off power gating technique, it also decreases leakage currents in searching operations without reducing search time and destroying noise margin. An energy-efficient 256×144 TCAM array is designed in 65nm Berkeley Predictive Technology Model (BPTM), and the simulation results show the leakage power reduction is 70.7% and the energy metric of the TCAM macro is 0.047 fJ/bit/search.
|頁（從 - 到）||97-108|
|期刊||International Journal of Electrical Engineering|
|出版狀態||Published - 1 四月 2008|