Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs

Chin Yang Lo, Po Tsang Huang, Wei Hwang

研究成果: Conference contribution

摘要

Deep learning applications are deployed to both resource and energy constrained edge devices via compact and sparse CNN models. However, sparsity, feature sizes and filter shapes are widely varying in deep networks resulting in inefficient resource utilization and data movement. In this paper, an energy-efficient accelerator is proposed for compact sparse CNNs by a flexible hierarchical on-chip interconnection architecture, 32 PE tiles and 3D-SRAM. 3D-SRAM are utilized as distributed memory for PE-tiles to hold intermediate data between layers for reducing the energy consumption of off-chip DRAM accesses. Based on distributed 3D-SRAM, output stationary dataflow is adopted without data movement of partial sums among PEs. Therefore, the 32 PE tiles are connected through a configurable ring-based unicast global network with micro-routers, which decreases implementation cost compared to a typical router for a mesh network. Each PE tile is implemented by an all-to-all local network to support widely varying sizes, shapes and non-zero activation computations of compact sparse CNNs. Overall, the proposed accelerator achieves 509.8 inference/sec, 1860.5 inference/J and 383.3 GOPS/W with MobileNetV2, and improves the energy efficiency by a factor of 1.43x over a dense architecture.

原文English
主出版物標題Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面320-323
頁數4
ISBN(電子)9781728149226
DOIs
出版狀態Published - 八月 2020
事件2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020 - Genova, Italy
持續時間: 31 八月 20202 九月 2020

出版系列

名字Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020

Conference

Conference2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020
國家Italy
城市Genova
期間31/08/202/09/20

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  • 引用此

    Lo, C. Y., Huang, P. T., & Hwang, W. (2020). Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. 於 Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020 (頁 320-323). [9073944] (Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/AICAS48895.2020.9073944