Embedded memory module design for video signal processing

Tian-Sheuan Chang*, Chein Wei Jen

*Corresponding author for this work

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.

原文English
頁面501-510
頁數10
出版狀態Published - 1 十二月 1995
事件Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn
持續時間: 16 十月 199518 十月 1995

Conference

ConferenceProceedings of the 1995 IEEE Workshop on VLSI Signal Processing
城市Osaka, Jpn
期間16/10/9518/10/95

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