Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.
|出版狀態||Published - 1 十二月 1995|
|事件||Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn|
持續時間: 16 十月 1995 → 18 十月 1995
|Conference||Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing|
|期間||16/10/95 → 18/10/95|