The electrical properties of the metal-ferroelectric-insulator-silicon memories with stacked gate configuration of Pt/SrBi2Ta2O9 (SBT)/Si3N4/p-Si (100) were investigated. In an attempt to operate at low voltage with sufficient large memory window, various ultra-thin Si3N4 buffer layers in thickness of 3.5, 2, and 0.9 nm were employed. From the results of C-V measurements, the memory window can be as large as 0.8 V at the bias amplitude of 5 V for the sample with 0.9 nm SixNy buffer layer. Well-crystallized perovskite structures have been further confirmed by the spectra of X-ray diffraction measurements. The leakage current, which plays a very important role in the data retention, of Pt/SBT (245 nm)/Si3N4 (0.9 nm)/p-Si (100) can be as low as 2.5 × 10-8 A/cm2 at 200 kV/cm. Excellent fatigue-free performance with up to 1010 read/write cycles and good retention time of >2 h have been obtained. Optimization and scaling of SBT thin films are believed to be effective in pursuing extremely low voltage operation, high-density and liable 1T nonvolatile ferroelectric random access memories.