Electrical properties of low-temperature-compatible P-channel polycrystalline-silicon TFTs using high-κ gate dielectrics

Ming Jui Yang*, Chao-Hsin Chien, Yi Hsien Lu, Chih Yen Shen, Tiao Yuan Huang

*Corresponding author for this work

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO2 and HfSiOχ high-κ gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-κ gate dielectrics exhibited superior device performance in terms of higher on/Ioff current ratios, lower subthreshold swings (SSs), and lower threshold voltages (Vth, relative to conventional deposited-SiO2, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiOχ as the gate dielectric had ca. 1.73 times the mobility (μFE ) relative to that of the deposited-SiO2 TFTs; in contrast, the HfO2 TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO2 TFTs. The immunity of the HfSiOχ TFTs was better than that of the HfO2 TFTs-in terms of their Vth shift, SS degradation, SS degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiOχ, rather than HfO2, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.

原文English
頁(從 - 到)1027-1034
頁數8
期刊IEEE Transactions on Electron Devices
55
發行號4
DOIs
出版狀態Published - 1 四月 2008

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