Efficient memory architecture for motion estimation processor design

Eddie G. Tzeng*, Chen-Yi Lee

*Corresponding author for this work

研究成果: Conference article同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.

原文English
頁(從 - 到)712-715
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
1
DOIs
出版狀態Published - 1 一月 1995
事件Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
持續時間: 30 四月 19953 五月 1995

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