摘要
This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.
原文 | English |
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頁(從 - 到) | 712-715 |
頁數 | 4 |
期刊 | Proceedings - IEEE International Symposium on Circuits and Systems |
卷 | 1 |
DOIs | |
出版狀態 | Published - 1 一月 1995 |
事件 | Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA 持續時間: 30 四月 1995 → 3 五月 1995 |