Efficient memory architecture for motion estimation processor design

This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.