Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's

Ming-Dou Ker*, Chung-Yu Wu, Tao Cheng, Hun Hsien Chang, Michael J.N. Wu, T. L. Yu

*Corresponding author for this work

研究成果: Paper同行評審

摘要

A novel square-type layout style is proposed to efficiently implement CMOS output buffer with larger W/L ratio into a smaller silicon layout area than that of conventional finger-type layout style. Using this proposed layout style, the driving capability of CMOS output buffer in low-voltage submicron CMOS IC's can be effectively improved without increasing more layout area.

原文English
頁面193-195
頁數3
出版狀態Published - 1 十二月 1995
事件Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China
持續時間: 24 十月 199528 十月 1995

Conference

ConferenceProceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology
城市Beijing, China
期間24/10/9528/10/95

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