Efficient hardware architecture of ηT pairing accelerator over characteristic three

Szu Chi Chung, Jing Yu Wu, Hsing Ping Fu, Jen Wei Lee, Hsie-Chia Chang, Chen-Yi Lee

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

To support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of ηT pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller's loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computation cost of final exponentiation. Pipelining and parallelization datapath are also exploited to shorten the critical path delay. Finally, by choosing suitable multiplier architecture and selecting an appropriate number of multipliers, Miller's loop and final exponentiation can be computed in a fully pipelined manner. With these schemes, a test chip for the proposed pairing accelerator has been fabricated in 90-nm CMOS 1P9M technology with a core area of 1.52 × 0.97 mm2. It performs a bilinear pairing computation over F(397) in 4.76 μs under 1.0 V supply and achieves 178% improvement to relative works in terms of area-time (AT) product. To support higher level of security, a 126-bit secure pairing accelerator that can complete a bilinear pairing computation over F(3709) in 36.2 μs is implemented and this result is at least 31% better than relative works in terms of AT product.

原文English
文章編號6744586
頁(從 - 到)88-97
頁數10
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
23
發行號1
DOIs
出版狀態Published - 1 一月 2015

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